From Ira Feldman's blog
IEEE Semiconductor Wafer Test Workshop – Parametric / Scribeline Probing – Session Six (Tuesday)
Here are the highlights from Session Five – Signal Integrity of the 20th annual IEEE Semiconductor Wafer Test Workshop (SWTW) from Tuesday June 8th.
Jay Thomas, Grund Technical Solutions, LLC., “Probe Cards with Modular Integrated Switching Matrices”:
For the last 30 years, most scribeline parametric testing has been approximately 85% Current-Voltage (I-V) testing and 15% Capacitance-Voltage (C-V) testing. For these types of tests a 10 MHz bandwidth switch matrix has been sufficient.
However, some of the larger fabs such as HP, IBM, and Intel have started performing pulsed Current-Voltage (PIV) and electrostatic discharge (ESD) testing. These customers started this type of testing about four years ago unknown to Agilent & Keithley (the two largest DC parametric tester suppliers). This PIV and ESD testing requires high frequency switch matrices with 1 GHz bandwidth. [For more about ESD testing please see Jay’s second presentation below in this session.]
In addition as oxides have become very thin this has made them “leaky”, therefore there is also a need to run higher frequency measurements. Typically the matrix switch needs to be 5x to 10x the bandwidth of the desired test frequency. This is also driving the need for higher bandwidth matrix switches.
Grund has developed a modular stack of a mother board with daughter cards to provide a 1 GHz matrix switch called the Genus matrix system. This stack of printed circuit boards (PCB) sits above the probe card on the prober and provides the necessary high frequency interconnect to the parametric tester and other equipment (ESD source, oscilloscope, etc.).
Ray Robertazzi, IBM Research, “New Directions in Parametric and Defect Structure Testing”:
As feature sizes shrink at the 22 nm process node and below, the variability in basic process measurements increases. Therefore they need to rely on statistical methods instead of a single pass / fail measurement. These statistical methods require a significant numbers of measurements to be valid. However the linear increase in test time due to the additional measurements is unacceptable.
What is needed is the ability to perform a large number of parametric measurements in parallel. The DC parametric testers currently used have the required sensitivity to make measurements in below 1 pA however on only one or two channels. While typical high parallelism logic testers which have thousands of channels that can operate in parallel don’t have the accuracy to measure below 10 nA (i.e. they are four orders of magnitude worse than the parametric testers).
Therefore, Verigy developed a pA source measurement unit (SMU) for their 93000 test system. The Verigy team led by Kosuke Miyao developed a fully integrated solution to provide 100 channels to perform measurements in the 5 pA range. [Kosuke was one of the excellent project managers on the Docking Services team I managed at Agilent. Kosuke: it is always a pleasure to hear a customer gush about how happy they are at the end of a project.] In addition to the SMU, the solution included high parallelism parametric probe cards from JEM, a new low leakage tri-axial pogo tower, and integrated control software.
However, modern test systems suffer from the lack of ability to observe or validate results. In Ray’s opinion test systems are the most complex electromechanical systems every developed by man. IBM under estimated how difficult the validation portion of the project would be. The Verigy validation load board (VLB) was designed to calibrate the SMU in the test system and had no observability for external validation. So in order to validate the test system setup they built a pA diagnostic instrument which allows correlation with a HP 4073 parametric tester and provides National Institute of Standards and Technology (NIST) traceability.
After validating the solution, the system was release to production. In production it has demonstrated a 5x throughput improvement due to the high parallelism in testing and is currently limited by the prober speed.
Jay Thomas, Grund Technical Solutions, LLC., “Wafer Level ESD Probe Card Solutions”:
Production testing of electrostatic discharge (ESD) test structures is a new market. In the past, ESD testing was previously done off line using a manual probe system. Neither Agilent (where he managed parametric testing applications) nor Keithley (to the best of his knowledge) support this in an automated fashion.
The traditional Human Body Model (HBM) provides a high voltage 2 A pulse with a 500 nS decay by discharging a 100 pF capacitor with a 1500 Ohm resistor. [Similar to the shock from running your feet across the carpet then touching another object.] However, the new European standard (required for CE marking) is the Human Metal Model (HMM). The HMM combines the HBM with a Charged Device Model (CDM) to simulate the discharge that might occur from holding an insulated screw driver. His presentation has scanning electron microscope (SEM) images of the different types of damage that is seen based upon the discharge model used.
Companies put ESD test structures in the scribe lines to predict how well the ESD protection circuits will work. Typically the ESD discharge takes place “off line” on an ESD “tester” (actually a discharge setup typically on a manual prober). Then the wafer is put back in the wafer prober and the test structure is tested using a DC parametric tester. Similarly to test actual parts you need to zap the part on the ESD “tester” and then need to test the part with a standard digital/mixed-signal tester to see if it survived. One example shown was a Hanwa system for CDM (about $250K). However, it needs to zap the pins one at a time. And on a 3,000 pin ball grid array (BGA) that would take some time to accomplish.
Through the use of the Genus matrix system (described above in Jay’s first presentation), they are able to integrate ESD discharge equipment in to the parametric test setup. This allows the “zapping” of the test structure and testing of it in an automated fashion without moving the wafer to an offline setup.
Note: I will post the link for the slides once they become available.
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